Real-Time Systems Design and Analysis (eBook, PDF). Tools for the Practitioner. Leseprobe · Real-Time Systems Design and Analysis (eBook, PDF) - Laplante. The leading guide to real-time systems design-revised and updated. This third edition of Phillip Laplante's bestselling, practical guide to. View Table of Contents for RealTime Systems Design and Analysis. Real‐Time Systems Design and Analysis: Tools for the Practitioner, Phillip A. Laplante · Seppo J. Ovaska PDF · Request permissions · xml.
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Laplante, Phillip A. Real-time systems design and analysis: an engineer's handbook / Phillip A. Laplante.–3rd ed. p. cm. Includes bibliographical references and. REAL-TIME SYSTEMS. DESIGN AND ANALYSIS. Tools for the Practitioner. Fourth Edition. PHILLIP A. LAPLANTE. SEPPO J. OVASKA. IEEE PRESS. A JOHN. Real Time System 12 Philip A Laplante 2nd Edition - Free download as PDF File .pdf), Text File .txt) or read online for free. For more notes on engg and CA visit.
Executing state. Terry Baker. A decision problem that is similar to an NP-completeproblem exceptthat for the NP-hard problem not even an exponential time solution can be found. SofnuareReliability and Testing,Piscataway,N. Old Password. Embedded versus loosely coupled versus organic of 1, above: Although numerous computers likely work on returns, the average processing time would need to be better than 1 per second, with.
Ovaska developed control systems for high-rise elevators; those contributions led to nine international patents.
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Skip to Main Content. Tools for the Practitioner , Fourth Edition Author s: Phillip A. Laplante Seppo J. First published: Print ISBN: About this book The leading text in the field explains step by step how to write software that responds in real time From power plants to medicine to avionics, the world increasingly depends on computer systems that can compute and respond to various excitations in real time.
This fully updated edition includes coverage of the following concepts: Multidisciplinary design challenges Time-triggered architectures Architectural advancements Automatic code generation Peripheral interfacing Life-cycle processes The final chapter of the text offers an expert perspective on the future of real-time systems and their applications. A patch that fits into the memory spaceallocatedto the code to be changed.
Input space. The set of all possibleinput combinationsto a system. Instruction register. CPU intemal register that holds the instruction pointed to by the contents of the program counter.
The processof uniting modules from different sourcesto form the overall system. Internal fragmentation. Condition that occurs in fixed-partition schemeswhen, for example, a processrequires I kilobyte of memory, while the only 2-kilobyte partitions are available. A hardware signal that initiates an event. Interrupt handler. Specialcode usedto respondto intemrpts. Also called an interrupt service routine.
Interrupt-handler location. Memory location containing the starting address of an interrupt-handlerroutine. The program counter is automatically loaded with its address when an interrupt occurs. Interrupt latency. The delay between when an intemrpt occurs and when the CPU begins reacting to it. Interrupt register. Register containing a bit map of all pending latched interrupts.
Interrupt return location. Memory location where the contentsof the program counter is saved when an intemrpt is processedby the CPU.
Interrupt vector. Register that contains the identity of the highest-priority intemrpt request. Intrinsic function.
A macro where the actual function call is replaced by in-line code. J Jackson Chart. A form of structure chart that provides for conditional branchins. K Kalrnan filter. A mathematical construct used to combine measurementsof the same quantity from different sources.
The smallestportion of the operating system that provides for task scheduling, dispatching, and intertask communication. A methodusedin real-timeUNIX in cails to kemel functionsto allow them to be intemrpted' usedto protect a critical region' Key.
In a mailbox, the data that are passedas a flag. L Leaf. Any node in a tree with no subtrees' pagereplacementalgorithm' Least recently used rule. The best nonpredictive a diagramat a finer level of Leveling. A processororganizedso that type can be executedin Parallel' Linker. Softwarethatpreparesrelocatableobjectcodeforexecutton' averagenumberof customersin Little,s law. Rule trom queuingtheory statingthat the aqueuingSystem,N"',isequaltotheaverageanivalrateofthecustomerstoth ta"' system,ru,, times the averagetime spentin that system' in the program' Live variable.
A variablethat can be used subsequently Livelock. Another term for process starvatron' the machine' Load module. Code that can be readily loaded into if you examine a list of recently executed Locality-of-ret'erence. When a systementersin which it is rendered Look-uptable. Anintegerarithmetictechniquethatusestablesandrelieson functions quickly' mathematicaldefinition of the derivative to compute computationsoutsidea loop that Loop invariant optimization.
The processof placing do not need to be performed within the loop' Looselycoupledsystem. Asystemthatcanrunonotherhardwarewiththerewri certainmodul: See leastrecentyusedrule'.
M computer operations'Also called Machine code. Binary instructions that affect specific machine language. See macroinstruction' Macroinstruction. Binary program code stored in the main memory of the computer' Also called macrocode. The largestsequence MAR. See memory addressregister' enabling or di'abling sFecric Mask register. A register that contains a bit map either intemrPts. Master processor. SeememorYdata register. Registerthat holds the address location to be acted on.
Registerthat holds the data to be is read fiom the memory location held in the MAR'. The percentageof usablememory that is being used' parts of a Memory locking.
Used in CRC seeChapter 11 ' on objects. In object-orientedsystems,functionsthat can be performed MFT. Multiprogrammingwith a fixed number of tasks' particular macro- Microcode. A sequenceof binary instructionscorrespondingto a instruction. Also called microinstructions' Microcontroller.
A computersystemthat is programmablevia microcode. See microcode. Sequenceof microcodestoredin micromemory' Minor cycle. A sequenceof repeatingprocessesin cyclic or periodic systems' with the Mixed listing. A printout that combinesthe high-orderlanguageinstruction equivalentassemblylanguage code' frequencies and Mixed system.
A system in which interrupts occur both at fixed sporadically" with high- Multimedia computing. Computing that involves computer systems resolution graphics, CD-ROM drives, mice, high-performancesound cards, and multitasking operating systemsthat support these devices' Multip exer.
An operating system in which more to provide for simultaneity; contrast with multitasking operating processoris available sysrcm.
An operating systemthat provides sufficient single processor so that the illusion of ality to aiow multiple programs to run on a simultaneity is created; contrast with multiprocessing operating system. A common name for a semaphorevariable' MUX. See multiPlexer' MVT. N Nano-kernel.
Code that provides simple thread-of-execution same as "flow-of- control" management;essentiallyprovides only one of the three servicesprovided by a kernel-that is, it providesfor task dispatching. Nonfunctional requirements. System requirementsthat cannot be tested easily by program executron. Nonvolatile menory. Memory whose contentsare preservedupon removing povl'er.
Non-von Neumann architecture. An architecturethat doesnot use the storedprogram, serial fetch-executecycle. A macroinstruction that does not changethe state of the computer. NP-complete problem, A decisionproblem that is a seeminglyintractableproblem for which the only known solutions are exponentialfunctions of the problem size; compare with NP-hard. A decision problem that is similar to an NP-completeproblem exceptthat for the NP-hard problem not even an exponential time solution can be found.
The composition of a reliability matrix with itself n - l trmes.
N-version programming. A techniqueusedto reducethe likelihood of systemlock-up by using redundantprocessors,each running software that has been coded to the same specificationsby different teams. A specific collection of machine instructions. Object-oriented language. A languagethat provides constructsthat encouragea high degree of information hiding and data abstraction. Starting addressof the microcode program stored in micromemory.
Operating system. A unique collection of systemsprograms. Organic system. A system that is not embedded. Orthogonal process. In statecharts,the combined functionalit. Orthogonal product. In statecharts. Ostrich algorithm. A techniquethat advisesthat the problem of deadlockbe ignored. Output space. The set of all possibleoutput combilations ior a s 'stem' Overlay. Dependentcode and data sections used in overlaf i,ng.
A technique that allows a srngle program to be larger than the allowable user space. Oversized patch. A patch that requires more memor - than is curendy occupied by the code to be replaced.
P Page. Fixed-sizechunk used in demand-pagedsystems. Page fault. An exceptionthat occurs when a memory referenceis made to a location within a page not loaded in marn memory. Page stealing. When a page is to be loaded into main memory, and no free pagesare found, then a page frame must be written out or swappedto disk to make room. Page table. A collectionof pointersto pagesusedto allow noncontiguousallocationof page frames in demandpaging.
Parnas partitioning. See information hiding. Partial order relation. In processscheduling,an indicator that any processcan call itself reflexivity ; if processA calls process B, then the reverse is not possible antisymmetry ,and if processA calls processB and processB calls processC, then processA can call processC transitivity. The processof correctingerrors in the code directly on the targetmachine. See program counter.
See program design language. An optimizationtechniquewhere a small window of assembly langageor machinecode is comparedagainstknown pattemsthat yield optimization opportunltles.
Pend operation. Operationof removing datafrom a mailbox. If data are not available, the processperforming the pend suspectsitself until the data becomeavailable. Petri net. Phase-driven code. See state-drivencode. An intertaskcommunicationmechanismprovided in UNIX. A techniqueused to speedprocessorexecutionthat relies on the fact that fetching the instruction is only one part of the fetch-execute cycle, and that it can overlap with different parts of the fetch-executecycle for other instructions.
Polled loop system. A real-timesystemin which a single and repetitivetest instruction is used to test a flag that indicates that some event has occurred. In object-oriented programming, polymorphism allows the pro- grarnmerto createa single function that operateson different objects dependingon the type of object involved.
Post operation. Operationthat placesdata in a mailbox. Power bus. The collectionof wires usedto distributeDowerto the variouscomponents of the computersystem. In certainprogramminglanguages,a pseudo-opthat allows assemblycode to be placed in-line with the high-order language code.
A condition that occurs when a higher-priority task interrupts a lower-priority task. Preemptive priority system. Primary memory. See main memory. Priority ceiling protocol.
A method used in interruptdriven systemsto avoid priority inversion;dictatesthat a task blocking a higher priority task inheritsthe higherpriority for the duration of that task.
Priority inversion. A condition that occurs becausea noncritical task with a high execution rate will have a higher priority than a critical task with a low execution rate. Subsysterrsused to calculatethe overall systemreliability. The individual processorsin a multiprocessingsystemsuch as a systolic or wavefiont architecture. Program counter. The CPU internal register that holds the address of the next instructionto be executed.
Program design language. A type of abstracthigh-order languageused in sYstem specification. Propagation delay. The contributionto interruptlatencydue to limitation in switching speedsof digital devicesand in the transit time of electronsacrosswires. A mock-up of a softwaresystemoften used during the designphase. A type of program design language.
R Raise. Mechanismused to initiate a softwareinterrupt in certain languagessuch asC. RAM scrubbing. A technique used in memory configurations that include error detectionand correctionchips.
The technique,which reducesthe chanceof multiple bit errorsoccuring,is neededbecausein someconfigurationsmemory effors are corrected on the bus and not in mernoryitself. The correctedmemory datathen needto be written back to rnemory. Random variable. A function mapping elements of the sample space into a real number.
Rate-monotonic system. A fixed-rate,preemptive,prioritized real-time systemshere the priorities are assignedso that the higher the executionfrequency,the higher the priority.
Reactive system. A systemthat has some ongoing interactionwith its enrironment. Logic line that is set to logic 0 during memory-u'rite and to logr. I during memory read. Ready state. In the task-controlblock model, the stateof those thsksthat are r Real-time system.
A system that must satisf;- explicit tbcundea': Recovery block. Sectionof code that terminate. A methoduherebya procedurecan be self-relerentiiri. Reduced instruction set cornputer.
Architecture usually characterizedby a small instruction set with limited addressing modes and hard-wired as opposed to microcoded instructlons. Reduction in strength. Optimization techniquethat usesthe fastestmacroinstruction possibleto accomplisha given calculation. Re-entrant procedure. A procedurethat can be usedby severalconcurrentlyrunning tasksin a multitaskingsystem. Register direct mode instruction. Instruction in which the operand field is a reglster.
Register indirect mode instruction. Instructionin which the operandaddressis kept in a registernamed in the operandfield of the instruction. A test methodologyused to validate updatedsoftu,areagainstan old set of test casesthat have alreadybeen passed. Reliability matrix. In a multiprocessingsystem,a matrix that denotesthe reliability of the connectionsbetweenprocessors.
The time between the presentationof a set of inputs to a software systemand the appearanceof all the associatedoutputs.
ReversePolish notation. The result of building a binary parsetree with operandsat the leavesand operationsat the roots, and then traversingit in post-orderfashion. Ring buffer. Data are loaded at the tail and read from the head.
See reducedinstructionset computer. In overlaying memory management,the portion of memory containing the overlay managerand code common to all overlay segments,such as math libraries. Round-robin system. A systemin which severalprocessesare executedsequentiallyto completion,often in conjunctionwith a cyclic executive. Round-robin system with time-slicing. A system in which each executabletask is assigneda fixed time quantumcalled a time slice in which to execute.
A clock is used to initate an interrupt at a rate correspondingto the time slice. S Sample space. The set of outcomesto some experiment.
Sampling rate. The rate at which an analog signal is converted to digital form. Scale factor. A technique used to simulate floating point operations by assigning an implicit noninteger value to the least significant bit of an integer.
Source code control system for managementof system code; typical for UNIX operatingsystems. Schedualability analysis. The compile time prediction of execution time per- formance.
The part of the kernel that determineswhich task will run. Scratch pad memory. CPU intemal memory used for intermediate results. Memorythatischaracterizedbylong-termstoragedevicesSucha tapes,disks, and cards' S e l f - m o d i f y i n g c o d e ' C o d e t h a t c a n a c t u a l l y c h a n g e i t s e lmay f ; f o rdiffer e x a mby p lonly e ' b yone taking of certain initructions advantageof tn" tu",iiat the opcodes bit.
A special variable on a semaphor' two operations that can be performed Semaphore primitives' The namelY,wait and signal' coupled system' Semidetachedsystem' See loosely S e n s e l i n e. D ein p ethe n d sense ingonth in the core, a pulse or is not generated orientation of the magnetrcfield line. A that must be used to comPletion' Server. Aprocessusedtomanagemultiplerequeststoaseriallyreusableresource SEU. Seesingleevent upset' as C' provided by certainlanguages'such Signal.
Exception-handlingmechanism Signaloperation. Alterationofmemorycontentsduetochargedparticlesprese event' Jpu"", ot in the presenceof a nuclear S aveprocessor. Repairable alteration Softreal-timesystem. Asysteminwhichperformancersdegradedbynotdestroye failure to meet responsetime constrarnts' Software. A collection of macroinstructlons' Softwarereliability. Theprobabilitythatasoftwaresystemwillnotfailbeforesom time t. Another name for with all interruptsocculrlng sporadicarir' Sporadic system.
A system by an interrupt that occursapen'rir'i'i Sporadic task. A task driven Spuriousinterrupts. Static random-access structure' Stack. A first-inAast-out data Stackmachines. A condition that occurs when a task is not being serviced frequently enough. State-driven code. Programcode basedon a finite stateautomaton.
Static memory. Memory that does not rely on capacitivechargeto storebinary data. Statistically based testing. Techniquethat usesan underlyingprobability distribution function for each systeminput to generaterandom test cases. Status register. A registerinvolved in interuptprocessingthat containsthe value of the lowest interrupt that will presentlybe honored. A type of testingwherein the systemis subjectedto a large disturbance in the inputs for example,a largeburstof interupts , foilowed by smallerdisturbances spreadout over a longer period of time.
Structure chart. Graphicaldesign tool usedto partition systemfunctionality. In the task-controlblock model, those tasks that are waiting on a particularresource,and thus are not ready. Also called the blocked state. The simplest schemethat allows the operating system to aliocate main memory to two processessimultaneously.
Switch bounce. The physical phenomenonthat an eiectricai signal cannot instanfa- neouslychangefrom its logical false condition. Synchronous data. Synchronous event. Event that occursat predictabletimes in the flow-of-control. Syndrome bits. The extra bits neededto implementa Hamming code. An entity that when presentedwith a set of inputs produces outputs. System programs.
Softwareused to managethe resourcesof the computer. System unification. A process consisting of linking together the testing software modulesin an orderly fashron. Systotic processors. Multiprocessingarchitecturethat consistsof a large number of uniform processorsconnectedin an array topology. T Task-control block. A collection of data associatedwith a task including processcode or a pointer to it , and other infonnation.
See task control block. A form of virtual reality in which a human operatorcan remotely control robots or other devicesas if the operatorwere physically present. Temporal determinism. A conditionthat occurswhen the responsetime for eachset of outputsis known in a deterministicsystem. Temporal fault tolerance. Techniquesthat allow for toleratingmisseddeadlines.
A macroinstructionthat can atomically test and then set a panicular memory addressto some value. Test probe. A checkpointused only during testing' Test suite. A collection of test cases. Very high paging activity. A measureof the number of macroinstructionsper secondthat can be processedbasedon some predeterminedinstructionmix.
The percentageof "useful" processingthe computer is doing. Also known as the utilization factor. Time overloaded. A systemthat is l00oloor more time-loaded. Time-relative data. A iollection of data that must be time correlated, Time-slice. A fixed time quantum used to limit execution time in round-robin systems. A transmitheceivehybrid device. A fully self-sufficient, multiple instruction set, von Neumann processor, designedto be connectedto other transputers.
Internal interrupt causedby the execution of a certain instruction. A high-impedancestate that, in effect, disconnectsa device from the bus. U Unit. A softwaremodule. Unreachable code. Code that can never be reachedin the normal flow-of-control. User space. Memory not required by the operating system. Utilization facator. See time-loadine. See linear iuray processor. This can catch potential problems or identify areas that need improvement early on in'the life cycle, when changes are made more easily and are less costiy.
It also increases communication between the users and the developers throughout the design process. Priorities ShOuid be assigned to aircraft depending on their position. Poiled loop code of Example 6.
Synchronized polied ioop code in C: State—driven code in C: Interrupt driven processes should be allowed to interrupt themselves in most cases. Although this may seem odd, there are practical reasons for it. By allowing a process to interrupt itself and by checking for this eventuality by checking and setting a globai flag at the start of the interrupt service routine , transient overloads.
The size of the stack should be the amount of space needed to save the state of one cycle, times the total number of cycles plus one. In this case, the background requires milliseconds to complete. If the background process has been operating for more than 25 milliseconds before being interrupted, then it will need oniy milliseconds to complete. If it is implemented in a direct access manner, then the size has no effect on the performance.
On the other hand. A large N'can seriously degrade real-time performance. If interrupts are disabled before the while statement in wait operation and the semaphore is iocked , then there will be no opportunity for another task to interrupt and release the semaphore. Hence, the process that is waiting will be hung up, and no other process can runw—a deadlock. I Chapter 8 - I 23 waittmutexi; extracttmailhox,messege i update; eignaltmutex ; end and Now, 7f.
Similarly, 7b. Moreover, since a queue is simply a mailbox with multiple entries, 7d. The only problem left is to implement a queue; all the rest follows easily.
And queues can be implemented by combining a counting semaphore and mailboxes. Allowing the signal Operation to be interrupted may prevent the interrupting task from accessing the critical section, even though it is still available since the signal operation was not able to reset the semaphore. The fact that a processor is blocked when waiting for the bus is not unusual e.
The best way to improve this situation is to implement a mailbox across the processors. In the given example reference string, for a four-page memory system, FIFO and LRU have the same number of page faults a fault at each memory reference. This can be seen by analyzing the system and noting that the same page replacements will take place for both algorithms, since no pages in memoery are ever re-used. Burst time: The problem should read that the consumer and producer processes have constant rates.
Since pm and C t are constant, denote them P and C, respectively. Equation