Power electronics pdf book

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main power converter topologies in Chapter 2, this book focuses primarily on con - power electronics converters that process ac voltage; additionally. Book News by Marian P. Kazmierkowski and Fernando A. Silva Grid Converters and Power Electronics Grid Converters for Photovol- 4) grid synchronization in. Power electronics is defined as the application of electronic devices and under the title Switched Mode Power Conversion is presented in this book [14].

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PDF Drive is your search engine for PDF files. As of today we have 78,, eBooks for you to download for free. No annoying ads, no download limits, enjoy . Books. Contacts: Beatriz Vieira Borges (responsável) email:b[email protected] Power Electronics Converter. Electrical. Source. DC or AC. POWER. CIRCUIT. PDF | On Aug 1, , Kandasamy kv and others published Power Electronics. Book · August with 11, Reads. Publisher: Sri.

This feature is used to reduce the switching losses in any application. Therefore the converter has ideally no losses. There are several drive circuits, which satisfy these requirements. The gate and emitter form the control terminal pair. These are suitable for circuits where low conduction loss is de- sired. The dielectric of the capacitor has a thermal resistance of 0. By Rajesh Pindoriya.

Switching Characteristics of a Bipolar Junction Transistor 1. The impor- tant features are Turn On To turn-on the device a forward base drive is established. The rise of collector current with time during hatched region 1 this transient is decided by the external circuit. During this storage time, ic continues to flow and the device voltage vce drop remains low. This is the time taken to remove the accumulated charge in the junction, so that the junction may start blocking.

The storage time increases with ib1 and decreases with ib2. During the fall time hatched region 2 , the collector- emitter voltage vce t is decided by the external circuit. It may be seen from the switching process that the device losses are low during the transient intervals td and ts. The switching losses occur during tr and tf. The collector current during tr and the device voltage during tf are dictated by the external circuit. This feature is used to reduce the switching losses in any application.

It is a three terminal device - drain D , source S and gate G. Drain and source form the power terminal pair. Source and gate form the control terminal pair.

The gate is insulated from the rest of the device and therefore draws no steady state current. Current flow then becomes possible across the drain and the source.

Whenever the gate to source voltage is zero, the device blocks.

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The N channel versions are more common. The device has no reverse blocking capability on account of the body diode, which conducts the reverse current. The peak and the continuous drain current are limited. Further the switching times are atleast an order of magnitude better than those of BJT. The conduction, blocking, and switching losses raise the junction temper- ature of the device.

The device needs a drive circuit. However the drive energy is smaller compared to a BJT because the steady state gate current requirement is zero. The MOSFET blocks positive voltage and passes both positive and neg- ative current negative current through the body diode.

The turn-on delay time td on is the time for the gate source capacitance to charge to the threshold level to bring the device into conduction. The rise time tr is the gate charging time to drive the gate through the control range of the gate voltage required for full condition of the device. At turn-off, the process is reversed. The turn-off delay time is the time td of f required for the gate to discharge from its overdriven voltage to the threshold voltage corresponding to active region.

The fall time is the time required for the gate voltage to move through the active region before entering cut-off. The GTO, a 3 terminal 4-layer semiconductor device is similar in construction to the Thyristor.

The two-transistor model of the GTO is shown in Fig. The operating principle of a GTO, similar to the SCR is based on the regeneratively coupled switching transistor pair.

The GTO on account of its construction, unlike an SCR, behaves like a large number of small Thyristors on a common substrate, with common anodes and gates, but individual cathodes.

However, in the case of the GTO, it is possible to turn-off the device by passing a reverse gate current. The ratio of anode current that can be turned-off to the reverse gate current necessary to carry out successfully the turn-off process is called the turn-off gain.

The switching cycle of a GTO consists of four different phases. In the case of a Thyristor, a small gate current is adequate to initiate the regenerative switching on process. The conduction then spreads to a large silicon area. The on-state currents may be several thousands of amperes. The on state rate-of-rise-of-current, however, has to be limited to a few hundred amperes per microsecond.

GTOs, on the contrary require a much larger current to initiate the regenerative turn-on process. On account of the segmented construction of the cathode, all the individual thyristors turn-on simultaneously. The anode current may rise at the rate of a few thousand amperes per microsecond. Turn-on gate current may vary and be orders of magnitude higher compared to SCRs.

The on-state voltage is low. Surge current capability is high and the conduction loss is low. Conduction and Turn-off of GTO 1. The cathode current is then constricted to- wards the centre of each cathode segment, thus pinching off the cathode cur- rent. As the cathode current is pinched, the anode current falls rapidly. During the pinch-off process the active silicon area reduces. Further, the cathode cur- rent tends to get redistributed away from the extinguishing gate current.

This process takes place during the storage time. This process culminates with a rising anode voltage and a falling anode current. This process is shown in Fig. The GTO zone in Fig. The GTO structure is well suited for high-current pulsed applications on account of their large turn-on rate-of- rise-of-anode-current capability.

In the conduction state, the GTO is like a Thyristor. Extra care must be taken such that the GTO does not partially unlatch following turn-on.

This may happen in motor drive applications, where the load current may fall momentarily to a low value following turn-on. The continuous drive current is to overcome such eventualities. This is all the more important when the load current becomes negative, when the load current flows through the freewheeling diode.

In such a case the GTO returns to the off state. Then when the load current becomes positive, the GTO will not turn on. This need is highly temperature dependent. In the blocking state, the preferred gate bias is about -5V or lower. This may be as high as the rated gate-cathode voltage. The device behaves as a low gain BJT with open base. The collector and emitter form the power terminal pair.

The gate and emitter form the control terminal pair. The operating points are either in the saturation region ON state or in the cut-off region OFF state. With the gate emitter voltage above the threshold voltage, the control side MOSFET turns on and forward biases the output pnp transistor.

The trade-off is in the switching speed. Another important point to notice is the presence of a parasitic SCR in the device structure. This can lead to a latch-up of the device in the ON state. The hazard of latch-up existed in the first generation IGBTs. The features of the IGBT in switching applications are 1. Turn-on is improved by a fast rising voltage source drive with low series impedance.

Turn-off is improved by charging the gate to a negative voltage during OFF time. The IGBT blocks positive voltage and passes positive current. With an integral hybrid reverse diode the device can also pass negative current. Just as in a transistor, the current rise in region 1 and the voltage build up in the region 2 are determined by the external circuit.

It combines the rugged on state performance of the thyristors and the positive features of the turn-off behaviour of the transistor. The Gate-Commutated Thyristor is a semiconduc- tor based on the GTO structure, whose gate circuit is of such low inductance that the cathode emitter can be shut off instantaneously, thereby converting the device during turn-off to effectively a bipolar transistor.

In the conducting state the IGCT is a regenerative thyristor switch. It is characterized by high current capability and low on-state voltage. In the blocking state, the gate-cathode junction is reverse-biased and is effectively out of operation. The major difference with IGCT is that the device can transit from conducting state to blocking state instan- taneously. The GTO does so via an intermediate state as illustrated in Fig. In IGCT technology, elimination of the GTO zone is achieved by quickly diverting the entire anode current away from the cathode and out of the gate.

The device becomes a transistor prior to it having to withstand any blocking voltage at all. It is the pnp transistor of the IGCTs regener- ative transistor pair which blocks after the npn transistor has been turned off with unity gain.

On account of this unity gain turn-off, it is necessary for the gate drive circuit to handle the full anode current and to do so quickly. The key to IGCT design lies in very low inductance gate circuits. These may require coaxial devices and multilayer circuit boards. One more important feature of the IGCT is that it behaves more like a digital than an analog device.

There is no control of the rate-of-change-of-anode voltage or current from the gate. It can also be turned on like a transistor, when the NPN transistor is driven hard. Typically a hard turn-on IGCT exhibits a monotonically falling anode voltage, compared to a soft turn-on IGCT that exhibits an oscillatory drop in anode voltage during turn on. We have seen that the real power switching devices dissipate energy unlike the ideal switching devices. Unless these losses are carried away from the junction, the temperature of the device junc- tion will rise without limit and eventually destroy the device.

In this section we see the basics of the thermal process in the device. A PN Diode and its Thermal Model thus established may be used to design heat sinks for the device to limit the temperature rise of the device junction. Part of this heat generated at the junction increases the temperature of the junction and the rest flows out of the junction onto the case of the device and therefrom to the environment of the device.

J is the calorific equivalent of joule. The above differential equation relates the thermal behaviour of the junction, and when solved will give the junction temperature rise as a function of time.

However, if we consider transients of very small duration as happens in power switches during switching , P t may be considered constant. Then the temperature rise may be conveniently calculated. Power Switching Device Mounted on the Heatsink 1. In practice to validate our assumption that the case temperature is constant, the device is mounted on a massive heatsink as shown in Fig.

The thermal model may be extended as shown in Fig. Of particular interest is the current modern power device namely the insulated gate bipo- lar transistor IGBT. Eqivalent Circuit of the Thermal Model Darlington modules at the high power medium frequency end of the applica- tion spectrum.

With such technology, it has become possible to integrate the peripheral devices to be built into the power modules.

The different levels of integration achieved and achievable are shown in Fig. Different Levels of Integration in IPMs user with the additional benefits of equipment miniaturization and reduced design cycle time. They include gate drive circuit and protection circuits for short circuit protection, over-current protection, over-temperature protection, and gate drive under-voltage lockout.

IPM has sophisticated built-in protec- tion circuits that prevent the power devices from being damaged in case of sys- tem malfunction or overload. A fault output signal is provided to alert the system controller if any of the protection circuits are activated. This diagram also shows the isolated interface circuits and isolated control power supply that must be provided to the IPM.

If for any reason, this voltage falls below the specified under-voltage trip level, the power devices will be turned off and a fault sig- nal generated. Small glitches less than the specified tdU V in length will not affect the operation of the control circuit and will be ignored by the under- voltage protection circuit.

In order for normal operation to resume, the control supply voltage must exceed the under-voltage reset level U Vr. Operation of the under-voltage protection circuit will also occur during power up and power down situation. The system controller must take into account the fault output delay tf o. If the temperature of the base plate exceeds the over-temperature trip level OT , the internal control circuit will protect the power devices by dis- abling the gate drive, and ignoring the control input signal till the normal- temperature condition is restored.

The over-temperature reset level is OTr. The over-temperature function provides effective protection against overloads and cooling system failures. Tripping of the over-temperature protection is an indication of stressful operation. Repetitive tripping is an indication that the above symptoms exist.

When the current, through the IGBT exceeds the short circuit trip level SC , an immediate controlled shut down is initiated and a fault output is generated. The IPMs employ for short circuit protection actual current measurements to detect dangerous conditions. This type of protection is faster and more reliable than the conventional out-of-saturation protection schemes. It is necessary to reduce the time between short-circuit detection and short-circuit shut down.

In certain IPMs this time may be as small as ns. Tripping of the over-current and short-circuit protection indicates stress- ful operation of the IGBT. Repetitive tripping is to be avoided. High surge voltage occurs during emergency shut down, Low inductance bus bars and snubbers are essential. It is necessary to coordinate the peak current and the maximum junction temperature. In high power 3 phase inverters using single or dual type IPMs, it is a good practice to use six isolated power supplies.

In these high current applications, each low side device must have its own isolated control power supply in order to avoid ground loop noise prob- lems. Using bootstrap technique is not recommended for the control power supply. A typical interface circuit is shown in Fig. IPMs can be profitably employed in practically all of the power supply and drive applications listed below at appropriate power levels to achieve higher levels of integration.

Induction Oven 5. For the switching devices shown in Fig. The power converter in Fig. The source voltage is 50V. The inductor current is steady 5A without any ripple. On the v-i plane mark the operating points of the switches T1 P and T2 P.

T2 P may be realized by an uncontrolled diode. Realisation of T1 P and T2 P. The current through and the voltage across a power device is shown in Fig. Evaluate the average current and the rms current rating of the device.

Evaluate the conduction loss in the device. In an inverter, the current through the active device is measured and found to be as shown in Fig. Evaluate the average current rating of the switch. The switching frequency may be considered very high compared to the fundamental frequency of the output current. If the power device is a power transistor with a Vce drop of 1.

The Thyristor may be modeled during conduction to have a constant voltage drop of 1. Evaluate the average conduction loss in the device for this application. Loss Calculation. Figure 7 shows the periodic current through a power-switching device in a switching converter application. A Evaluate the average current through the device. B Evaluate the rms current through the device. C A BJT with a device drop of 1.

Evaluate the conduction loss in the device in either case. A disc type Thyristor is shown with its cooling arrangement in Fig. The device is operating with a steady power dissipation of W. Thermal Design. A Evaluate the steady state temperature rise of the junction. B With the above steady power dissipation of W, find the excess power dissipation allowable for 10 ms, if the junction temperature rise is not to exceed 90C.

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A power diode ideal in blocking and switching shown in Fig. For square wave operation, it is rated for peak current of A and A at duty ratios 0. Evaluate the ON state model of the diode. Evaluate the thermal resistances of the device. Assume ideal switching behaviour. B Evaluate the blocking loss in watts. D Evaluate the energy dissipation during the transitions. Switching Transients. A power-switching device is rated for V and 30A. The device has an on state voltage drop of 1.

The device has a leakage current of 5 mA while blocking V. Evaluate A the maximum conduction loss, B maximum blocking loss, and C ratio of the conduction and blocking loss with maximum possible power that may be controlled by this switch and make your comment on the result.

A power-switching device is ideal in conduction and blocking 0 V during conduction and 0 A in blocking. It is used in a circuit with switching voltages and currents as shown. The switching waveforms under resistive loading and inductive loading are shown in Fig.

The switching times tr and tf are ns and ns respectively. Switching Waveforms under Resistive and Inductive Switching A the switch-on and switch-off energy loss in Joule for resistive load- ing, B the switch-on and switch-off energy loss in Joule for inductive load- ing, and C the resistive and inductive switching losses in W for a switching fre- quency of kHz. The device carries a current as shown in Fig. Consider the switching process to be ideal and evaluate the conduction loss in the device.

It is necessary to evaluate the rms current through the device. Explore if you can simplify the evaluation of rms value by applying superposition. It has a voltage drop of 0. Fit a piece-wise linear model for this diode consisting of a cut-in voltage and dynamic resistance.

With this piece-wise model evaluate its conduction loss for a 30A peak half sine wave of current. Comment on this observation. The thermal process is predominantly a first-order process and is similar in most applications. The thermal model is related to the physical process of evacuation of heat to the ambient. This problem set is to apply the sim- ple steady state and transient thermal models to evaluate temperature rise, thermal resistance, temperature ripple, etc.

Evaluate the cooling time constant of the trans- former. Periodic Power Dissipation in the Switch 7. A power-switching device dissipates an average power of W and is mounted on a heatsink. Evaluate the case-to-ambient and junction-to-heatsink thermal resistances.

Figure 8 shows the periodic power dissipation in a power device. The junction-to-case and case-to-ambient thermal resistances are respectively 0. The thermal time constant is 0. Evaluate of the steady-state maximum and minimum temperature of the junction and the case. A heatsink has a radiation surface area of cm2 and convection surface area of cm2. The radiation dissipation constant is 0. The convection dissipation constant is 0. The heatsink has a mass of 0.

Evaluate the thermal resistance of the heatsink. Evaluate the thermal time constant of the heatsink. In the above problem, when the convection process is blocked, evaluate the thermal resistance and the thermal time constant of the heatsink. The thermal time constant of the device together with the heatsink is 1 s. Under this condition, evaluate the excess pulsed power of duration 0.

A composite switch Q1 and Q2 in parallel carrying a load current of 10A is shown in Fig. The switches may be considered ideal in switching. The on-state resistances of the devices Q1 and Q2 are respectively 0. C the junction temperatures of Q1 and Q2. The switch-on transition consists of two sub- intervals rise time of 0. A composite switch used in a power converter is shown in Fig. The periodic current through the switch is also shown.

Current Through the Device A the average current and rms current through the composite switch. Download the datasheet and fill in the following. A Manufacturer. B Device and Type No. C On-state voltage V. D Off-state current A.

E Transient switching times s. F Maximum junction temperature K. G Recommended drive conditions? H Conduction loss at rated current W. I Blocking loss at rated voltage W. J Switching energy loss J. In this section the basics of electromagnetics is reviewed. The type of capacitors popular in power electronic applications are also given. They are formulated in such a way as to be useful for the design of inductors and transformers.

Conduction Process 2. This law may be stated as follows. This is shown in Fig. Seen as an electrical circuit element, the electromagnetic element possesses the prop- erty of energy storage without dissipation.

Magnetomotive Force relate the electric and magnetic circuits of the electromagnetic element. For example for the electromagnetic circuits shown in Fig. Magnetic Equivalent Circuit in Fig. Thus an electromagnetic circuit provides us an electric circuit element inductor. The voltage across an inductor is directly proportional to the rate of rise of current through it. Electromagnetic Circuit parts may be conveniently represented as shown in Fig.

However in practice, the inductor will have certain parasitic resistance of the wire in the electric circuit and magnetic leakage in the magnetic circuit. These non-idealities may conveniently be incorporated in the equivalent circuit as shown in Fig. The design of an inductor involves the design of the electrical Number of turns and wire size and the magnetic geometry of the magnetic core and its required magnetic property circuit. Electromagnetic Circuit with Parasitics 2.

When this limit is exceeded, the wire will overheat from the heat generated I 2 R and melt or deteriorate. Any magnetic material can only carry a certain maximum flux density. When this limit is exceeded, the material saturates and the relative permeability drops substantially. This maximum allowable flux density for the magnetic material is denoted by Bm T.

Let the window area AW be filled by conductors to a fraction of kw. For copper conductors J is between 2. Select a core from core tables with the required AC AW. For the selected core, find AC , and AW. Check the assumptions: Compute from the geometry of the core, mean length per turn and the length of the winding. From wire tables, find the resistance of winding. Electromagnetic Circuit of a Transformer 2.

The transformer consists of more than one winding. Also, in order to keep the magnetization current low, the transformer does not have air gap in its magnetizing circuit. Consider a transformer with a single primary and single secondary as shown in Fig. Let the specifications be Primary: V1 volt; I1 ampere; Secondary: V2 volt; I2 ampere; VA Rating: Select the smallest core from the core tables having an area product higher than obtained in step 1.

Find the core area AC and window area AW of the selected core. Select the nearest higher whole number to that obtained in step 4 , for the primary and secondary turns. Compute the wire size for secondary and primary. Select from the wire tables the desired wire size. Compute the length of secondary and primary turns, from the mean length per turn of the core tables. Find from the wire tables, the primary and secondary resistance.

Compute from the core details, the reluctance of the core. Compute the magnetizing inductance. Design of Transformers and Inductors Laminations: GKW Core Section: Square Flux Density: A data book on cores and accessories is available at Magnetic Cores and Accessories. Unlike in signal conditioning applications, the capacitors in PES are required to handle large power.

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As a result they must be capable of carrying large current without overheating. To satisfy the demands in PES, the capacitors must be very close to their ideal characteristics namely low equivalent series resistance ESR and low equivalent series inductance ESL.

Low ESR will ensure low losses in the capacitor. Low ESL will ensure that the capacitor can be used in a large range of operating frequency. Figure 8 shows the impedance of a capacitor as a function of frequency. Impedance of a Capacitor as a Function of Frequency close to the ideal at lower frequencies. The current carried by such a capacitor is comparatively low. Coupling Capacitor 2. They compensate the re- active power demanded by the load so that the power handling portion of the PES are not called upon to supply the reactive power.

Further, they also bypass harmonics generated in the PES. In such applications the voltage is pre- dominantly sinusoidal; the current may be rich in harmonics.

A typical application is shown in Fig. Power Frequency Power Capacitors 2. Such applications arise when capacitor banks are switched on and off to cater to conditions of varying load typical in induction heating applications. They are called upon to handle large periodic currents.

Waveforms in a Filtering Application These capacitors are electrolytic capacitors on account of the unipolar voltage they are subjected to. Typical applications are shown in Fig.

Typical applications are precision welding, electronic photoflash, elec- tronic ignition etc. Pulse Capacitor Application 2. The rms current in the capacitor will be high. They are subjected to very high reactive power and peak currents. The commutation process is quite short and so these capacitors must have purely capacitive reactance even at high operating frequency. Damping Application ic t vc t Figure 2. Commutation Applications ic ic t vc t Figure 2. The operating frequency is high.

The stability of the capacitor is important. The following links give data sheets of different types of capacitors. Figure 1 shows the voltage across a capacitor used for a power electronic application.

The capacitance value is 2. The dielectric of the capacitor has a thermal resistance of 0. A Sketch the current waveform through the capacitor for one cycle. B Evaluate the losses in the capacitor. C Evaluate the temperature rise in the dielectric of the capacitor. A power electronic capacitor is specified to have the following values. The following design refers to a 2 mH inductor suitable for dc application with a maximum current of 0.

Figure 4 shows the magnetic circuit of a coupled inductor. The magnetic material of the core may be assumed to be ideal. Evaluate the inductances L1 , L2 , L12 , L The approximate wave shape of a capacitor current in a commutation circuit is shown in Fig. Evaluate the power dissipation in the capacitor. Figure 6 shows a lifting magnet used for handling metal billets in a steel mill. The dc current I to the coil of N turns is supplied from a current source.

The area of cross section of the magnetic path is Ae m2. The yoke of the magnet and the metal billet may be assumed to be infinitely permeable. The fringing effect of the field in the path of the magnet may be neglected. B Find the force exerted by the magnet as a function of the gap length. For x close to zero, infinite permeability assumption is not valid. Figures 7 a, b, and c show three magnetic circuits with an exciting winding on each having turns.

The core in c is obtained by as- sembling together one each of cores shown in a and b. The magnetic material for the core may be considered to have very large permeability with saturation flux density of 0. D Comment on the inductance of the circuit c.

Na Nb lga 0. Figure shows the magnetic circuit of a coupled inductor. Make suitable assumptions and evaluate the inductances La , Lb , and Lc. Figure 9 shows a coupled magnetic circuit. The two windings are excited by identical square waves. The core has a cross-sectional area of S unit. The reluctance of the central limb is Rc unit. The reluctance of the outer limbs are dominated by the gap reluctances. A Draw the equivalent reluctance circuit model of the magnetic circuit. B Find the self-inductances L11 and L E Write the dynamic equations relating vt , i1 t , and i2 t.

Interpret the result. The ideal requirements are set down and some of the practical circuits useful in achieving these requirements are given. Such high power transistors are quire sensitive to voltage and current stresses. The high voltage devices are very sensitive to reverse biased second breakdown.

The high current devices usually have low current gain. On account of these factors, the design of suitable drive circuits for BJTs is a demanding task. A steady base current of adequate magnitude IB to keep the device in saturation during the on period of the switch.

A base voltage of adequate negative magnitude typically 5V during the off period of the device. The drive circuit must be such that the switching performance is insen- sitive to the operating point of the switch. Electrical isolation between the control input and the switch may be de- sired.

This will be necessary very often when the system has several switches located at different electrical potentials. The drive circuit must have overriding protection to switch off the device under fault. Base drive current is zero under this condition. There are several drive circuits, which satisfy these requirements.

Some of these circuits are described here. Drive Circuit 1 3. The turn on time of the base drive is the same as the rise time of the control transistor TB. This is a very rudimentary circuit. The drive requirement 1 and 3 are satisfied by this circuit and is not a practical circuit. Drive Circuit 2 3. This drive circuit satisfies the requirements 1, 2, 3, and 4. This does not provide negative bias during the off period.

There is no electrical isolation or other protections. This circuit may be used in single switch chopper circuits. Drive Circuit 3 3. This would result in the switch being overdriven when the switch current is low. For applications where the load current is varying over a wide range, this may result in the storage delay time being a function of the load.

This delay time variation could cause difficulties especially at high switching frequencies the delay time may become appreciable compared to the on and off time of the switch. In such applications the excess base drive current may be diverted by a simple add-on circuit known as the Baker clamp. Drive Circuit 4 saturation, the Vce drop of the switch becomes low and forward biases Das. Thus the excess drive is diverted from the base into the collector.

Such a drive will keep the switch on the border of saturation, thereby making the storage delay time independent of the switch current.

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However this positive feature is obtained at the cost of higher conduction loss Note that the Vce drop now cannot go below about 0. The base drive shown in Fig. Such isolated drive circuits employing opto-couplers may be used upto a frequency of about 5 KHz.

Drive Circuit 6 3. In such applications optocoupler circuits will be too slow. Electromagnetic isolation is used then.

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A circuit with electromagnetic isolation capable of operating upto about 20 KHz is shown in Fig. The operating frequency range may be extended further if the SR flip flop is faster. Notice again the need for a separate isolated power supply. An elegant solution to this problem at high switching frequen- cies is the proportional drive circuit. The required power to drive the switch is drawn from the load circuit itself through a current transformer CT.

A typical proportional base drive circuit is shown in Fig. Drive Circuit 7 range of 20 to 50 KHz. Notice the absence of the Baker clamp. The antisatu- ration circuit is not required, since the base drive is proportional to the switch current. This circuit is especially useful for switches, which turn on at zero current many resonant converters. The control circuit is required to provide energy to only initiate the turn on and turn off process 3. The control circuit must be capable of cutting off the base drive when over current through the device is sensed.

This may be done directly with a Hall effect current sensor in series with the transistor or indirectly by sensing the collector-emitter voltage drop of the device during conduction. When the device is overloaded the current gain of the transistor will drop and as a result the device will come out of saturation. This will result in an increase in the collector-emitter voltage. A drive circuit, which senses the over current indirectly and cuts off the drive current to the transistor, is shown in Fig.

During the switch-on time the device voltage is defined. During switch-off the device cur- rent is defined. The second quantity during switching device current during turn-on and device voltage during turn-off is decided by the external circuit to the switch. Drive Circuit 8 inductive filters. The power circuit will have parasitic inductance associated with the conducting paths. Further there will be several other non-idealities of the switches present.

On account of all these factors, the switching process in the device will be far from ideal. Figure 10 shows a simple chopper cir- cuit consisting of all ideal components except the power switching device in this case a BJT.

The load being inductive, may be considered to be a con- stant current branch for the purpose of analysis.

The switch voltage, current, switching energy loss and the v-i trajectory of the switch current and voltage on the vi plane in course of switching are shown in Fig. The peak power dissipation in the device is seen to be quite large VG IL. The switching loci with some of these nonidealities are shown in Fig. The current overshoot 1 is on account of the reverse recovery current of the diode. The voltage overshoot 2 is on account of the stray inductances and capacitances in the circuit.

The important point to notice is that the peak voltage and current stresses on the switching device are far more than the circuit voltage and the load current. The switching loci traverse far from the axes of the v-i plane, thus indicating large transient losses.

When these loci cross the safe operating area of the v-i plane, device failure is certain. Switching Trajectories with Non-idealities in the Chopper vi axes during the switching transient. From the non-ideal switching loci, it may be seen that over currents occur during turn-on and over voltage during turn-off. The snubber ensures that during turn-on rate of rise of current is limited with a series inductor , and during turn-off the rate of rise of voltage is limited with a shunt capacitor.

The other elements in the snubber are to reduce the effects of turn-on snubber on the turn-off process and turn-off snubber on the turn-on process. The snubber circuit caters to three functions. It may be seen qualitatively that on turn-off the device current is diverted into the capacitor through Df so that the device voltage on turn-off is constrained to rise slowly. At the end of turn-off the capacitor is charged to the circuit voltage.

During the next turn-on the capacitor discharges its energy into the resistor Rf and is ready for the next turn-off. The snubber reduces the device turn-off loss by forcing the device voltage to rise slowly. But the energy trapped in the capacitor at the end of the turn-off process has to be lost in Rf during the next turn-on. From Fig. Turn-off Snubber Turn off loss without snubber: Turn-on Snubber Fig.

With Cf in the range of 0. The snubber capacitor Cf may be designed based on this criteria. After selecting Cf , Rf is chosen such that the Rf Cf time constant is much less than the minimum on time in the given application.

This will ensure that the snubber capacitor is reset during the on time and is ready for the next turn-off. It may be seen qualitatively that on turn-on, the excess voltage is dropped across the inductor Lo so that the device current on turn-on is constrained to rise slowly.

At the end of turn-on the inductor carries the load current and stores the associated energy.

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During the next turn-off the inductor discharges its energy into the parallel resistor Ro and is ready for the next turn-on. The snubber reduces the device turn-on loss by forcing the device current to rise slowly. But the energy trapped in the inductor at the end of the turn on process has to be lost in Ro during the next turn-off.

Turn off loss without snubber: With Lo in the range of 0. The snubber inductor Lo may be designed based on this criteria. This will ensure that the snubber inductor is reset during the off time and is ready for the next turn-on. Figure 15 shows a snubber circuit, which provides both turn-on and turn-off aid. Note that Rof serves as Rf and Ro.

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Dof serves as Do and Df. For many low power applications these snubbers are satisfactory. For higher power applications, it may be difficult to eliminate stray inductance in the power circuit. In such cases it will be necessary to provide over voltage protection. Over voltages are on account of current interruptions through the stray inductance in the circuit. Two snubber circuits which protect the device from switching over voltage with switch-on and switch-off snubbers are shown in Figs.

IL Figure 3. Snubber for a Pair of Complementary Switches 3. They are becoming popular now for low power applications. This will ensure low turn-on loss. Since the gate is isolated from the source, the current required to maintain the gate source voltage constant is zero.

This gate voltage that is applied during the off period must be through a low impedance to ensure good noise margin. This will be necessary very often when the system has several switches at different electrical potentials. The preferred gate drive is illustrated in Fig. The features are 1.

Fast rising gate current for fast turn on. Hard turn on drive to reduce turn on loss. Adequate gate voltage for low conduction loss. Negative gate drive for fast turn off. Negative base bias for good noise immunity. Some of these circuits are shown in Figs. Several commercially available drive circuits are given in the following links. The circuit shown below is a chopper operating at 10 kHz.

Evaluate the switching losses in the snubber of the circuit. The drive circuit shown is used to control the transistor switch S. The device S requires appropriate continuous positive base current during ON time and transient negative base current of atleast 1. Evaluate the values of R1, R2, and C. At nS, the gate voltage reaches 10 V. The following circuit is a simple non-isolated drive used with a BJT. The base emitter drop of the power transistor and the drive transistors Vbe are 0. The different parameters relating to the circuit are: The control input is as shown.

A Sketch the base current waveform. C Evaluate the peak current rating of the drive sources. Circuit 3. Equivalent Circuits and Drive Currents 6. The current through and the voltage across a switching device is given in Fig. Evaluate the approximate switch-off and switch-on energy loss in the device. The following problem is based on the analysis of snubber circuits for transistor switches. The circuits in Fig. The load L, C and R form the inductive load on the chopper.

The elements Lo , Do and Ro form the turn-off snubber. The following assumptions in the analysis of switching transients are valid. It is necessary to analyse the turn-on and turn-off transient during the switching process. The drive waveforms during the switch-off process are shown in Fig.

The circuit equivalents in the different intervals Pre-transient, turn-off storage delay time ts , fall time tf , turn-on com- pletion time T1 , T2 and T3 , and post-transient time. These intervals are marked sequentially as intervals 1,2,3,4,5,6 and 7.

Interval 1 is the pre- transient time. Interval 2 is the turn-off storage delay time. The effective turn-on transient starts in interval 3. In this interval, it may be taken that the voltage across the switch is given by! A During the interval 3, find the expressions for the following quantities as a function of time.

At the end of interval 3, the transistor is completely off. However, the transient process not complete. Artificial Neural-Network Applica- courses. Power Quality and Devices and Applications, 3rd ed. Simulation and Pack- Boca Raton, FL: Digital Object Identifier Related Papers. By Rajesh Pindoriya. The past, present, and future of power electronics [Guest Introduction]. By Bimal Bose. Guest Introduction. By juyoung sim. How power electronics contribute to the current energy arena.

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