Microcontrollers. PDF created with pdfFactory trial version soundofheaven.info . PIC16FA K. .. To obtain the most uputoudate version of this data sheet, please register at our Worldwide Web site at. PIC16FA datasheet, PIC16FA circuit, PIC16FA data sheet: MICROCHIP - 28/pin Enhanced FLASH Microcontrollers,alldatasheet, datasheet. PIC16F Datasheet PDF Download - PIC16F87X 28/Pin 8-Bit CMOS FLASH Microcontrollers Devices Included in this Data Sheet: • PIC16F
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Devices Included in this Data Sheet: PIC16FA K .. You can determine the version of a data sheet by examining its literature number found on the. IC datasheet. PIC16FA datasheet specifies that this CMOS FLASH-based 8-bit microcontroller packs Microchip’s powerful PIC architecture into an or pin package and is upwards compatible with the PIC16C5X, PIC12CXXX and PIC16C7X devices. download PIC16FA datasheet. Learn about PIC16FA PIC series microcontroller with its a detailed overview of PIC16FA features with its PDF datasheet to download.
Transmit Shift Reg. The prescaler is not specification of the desired device. Set the WREN bit to enable program operations. None Operation: This is a two-cycle placed in the W register. These registers can be addressed from any bank. If the Comparator Otherwise, a false interrupt may occur.
On power-up, WREN is cleared. External write access to the program memory Also, the Power-up Timer 72 ms duration prevents an is also disabled. When program memory is code-protected, the microcon- The write initiate sequence and the WREN bit together troller can read and write to program memory normally, help prevent an accidental write during brown-out, as well as execute instructions.
Writes by the device may power glitch or software malfunction. WR0 of the configuration word see Section External access to the memory is also disabled.
High-Impedance mode. All Data Data Latch write operations are read-modify-write operations. Buffer Q D The comparators are in the off digital state. Output is open-drain type. The corre- interrupt in the following manner: This will end the pin an input i. Debugger and Low-Voltage Programming function: The alternate wake-up on key depression operation and operations functions of these pins are described in Section A using the interrupt-on-change feature. The ware configurable pull-ups on these four pins, allow weak pull-up is automatically turned off when the port easy interface to a keypad and make it possible for pin is configured as an output.
The pull-ups are wake-up on key depression. Refer to the application disabled on a Power-on Reset. EN Q1 2: Only pins configured as inputs can RB7: RB4 pins EN cause this interrupt to occur i. RB4 pin Q3 configured as an output is excluded from the interrupt- RB7: RB6 on-change comparison.
The input pins of RB7: RB4 2: Internal software programmable weak pull-up. Serial programming clock. Serial programming data. This buffer is a Schmitt Trigger input when used in Serial Programming mode or in-circuit debugger. Each pin is individually configurable as an input Port CK or output. These pins have Schmitt Trigger CK input buffers. The user must make sure to keep the pins configured as inputs when using them as analog inputs. There are actually two 8-bit latches: Shaded cells are not used by the Parallel Slave Port.
Clearing bit T0SE selects the ris- ing edge.
The Figure is a block diagram of the Timer0 module and prescaler is not readable or writable. Section 5. Bit prescaler. PS0 PSA. WDT Time-out. This prescaler is not readable or writable see Figure The synchronization determine the prescaler assignment and prescale ratio. Therefore, it is writing to the TMR0 register e. Refer to the electrical along with the Watchdog Timer. The prescaler is not specification of the desired device.
Writing to TMR0 when the prescaler is 5. A prescaler assignment for the. This sequence must be followed even if the WDT is disabled. Shaded cells are not used by Timer0. This interrupt can be Section 8. Manual DS This bit is ignored.
After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment. The synchro- nization is done after the prescaler stage. In prescaler stage is an asynchronous ripple counter. This eliminates power drain. C1 C2 clock input is not synchronized. However, special precautions in These values are for design guidance only.
Crystals Tested: In Asynchronous Counter mode, Timer1 cannot be Higher capacitance increases the stability Reading TMR1H or TMR1L while the timer is running of oscillator but also increases the start-up from an external asynchronous clock will ensure a valid time. However, the user 2: A write conten- tion may occur by writing to the timer registers while the 6. This may produce an unpredictable value in the timer register.
Trigger Output Reading the bit value requires some care. Asynchronous mode. It is enabled by nized Counter mode to take advantage of this feature. The oscil- If Timer1 is running in Asynchronous Counter mode, lator is a low-power oscillator, rated up to kHz. It this Reset operation may not work. It is primarily intended In the event that a write to Timer1 coincides with a for use with a 32 kHz crystal. The Timer1 oscillator is identical to the LP oscillator.
CCPRxL regis- The user must provide a software time delay to ensure ter pair effectively becomes the period register for proper oscillator start-up. In all other Resets, the register is unaffected.
Shaded cells are not used by the Timer1 module. The TMR2 register is readable and writable and is cleared on any device Reset. TMR2 Reg 1: PR2 is Postscaler 2 Comparator 1: SSP module as a baud clock. Shaded cells are not used by the Timer2 module. The special event trigger is generated by a compare match and will reset Timer1.
Compare mode: PWM mode: An event is defined as one of the capture feature. In Asynchronous Counter mode, the following: When a cap- change in operating mode. The interrupt flag must be cleared in 8. Whenever the CCP module is overwritten by the new value. Any Reset will clear 8. Also, the prescaler counter will not be cleared, therefore, the first capture may be from Note: Example shows the recom- output, a write to the port can cause a mended method for switching between capture Capture condition.
In Asynchronous Counter mode, the compare operation may not work. At the a CCP interrupt if enabled. TMR1 register pair.
R Match. Since register. The Timer2 postscaler see Section 7. CCPR1L 8. In PWM mode, Note 1: This A PWM output Figure has a time base period double-buffering is essential for glitch-free PWM and a time that the output stays high duty cycle.
The operation. Shaded cells are not used by Capture and Timer1. The PSP is not implemented on pin devices; always maintain these bits clear. Shaded cells are not used by PWM and Timer2. SSPM0 9. Additional details are provided under the individual sections. The transmitted and received simultaneously.
These are: Sample bit SPI Master mode: Stop bit Used in I2C mode only. Start bit Used in I2C mode only. Update Address bit Used in I2C mode only. Must be cleared in software. Overflow can only occur in Slave mode. When enabled, these pins must be properly configured as input or output. SS pin control disabled. SS pin control enabled. Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
User software must clear specified. The not occur. This double-buffering of the received data SSPBUF allows the next byte to start reception before reading the data that was just received. Any write to the. To reset or reconfigure microcontrollers. For the pins to behave as the serial port func- edge of the clock. Both processors should be tion, some must have their data direction bits in the programmed to the same Clock Polarity CKP , then TRIS register appropriately programmed.
That is: Whether the data is meaningful or dummy data depends on the application software. Any serial port function that is not desired may be overridden by programming the corresponding data direction TRIS register to the opposite value.
In Master mode, the SPI clock rate The master can initiate the data transfer at any time bit rate is user programmable to be one of the because it controls the SCK. The master determines following: SDI pin at the programmed clock rate.
This could be useful in receiver there is a clock edge on SCK. This then, would give waveforms for SPI communication as shown in. When the may be desirable, depending on the application. While in Slave mode, the external clock is supplied by Note 1: When a byte is received, the device will wake-up set, then the SS pin control must be from Sleep. When the SPI module resets, the bit counter is forced 9.
The SS pin allows a Synchronous Slave mode. The pin must not be driven low operate as a receiver, the SDO pin can be configured for the SS pin to function as an input. The data latch as an input. This disables transmissions from the SDO. When since it cannot create a bus conflict. SDO bit 7 bit 6 bit 7 bit 0. After the device returns to CKE control bits. In Slave mode: In Master mode: Buffer Full Status bit In Transmit mode: Receive Overflow Indicator bit In Receive mode: Used to ensure data setup time.
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
Automatically cleared by hardware. All incom- tion. SCL line. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. To ensure proper operation MSbs of the first address byte specify if this is a bit of the module, pull-up resistors must be provided address.
For a bit address, the first byte would equal 9. The MSSP module bit address is as follows, with steps 7 through 9 for will override the input state with the output data when the slave-transmitter: Through the mode 2. When an address is matched, or the data transfer after 3. Receive Repeated Start condition. The 9. The SCL clock input must have a minimum high and low for proper operation.
The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter and parameter An overflow more detail. See Section 9. An MSSP interrupt is generated for each data transfer byte. ACK is not sent. By holding the SCL line 9. By holding 2: This will prevent buffer overruns from occurring see Transmit Mode Figure In bit Slave Transmit mode, clock stretching is con- trolled during the first two address sequences by the Note 1: After stretching will not occur.
The CKP bit can be set in software not set, the module is now configured in Transmit regardless of the state of the BF bit. The mode and clock stretching is controlled by the BF flag user should be careful to clear the BF bit as in 7-bit Slave Transmit mode see Figure During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. Clock stretching will occur on each data receive sequence as described in 7-bit mode.
Clock stretching, on the basis of the state of the BF bit, only occurs during a data sequence, not an address sequence. Master device asserts clock CKP. When the interrupt is serviced, the source for the inter- The exception is the general call address which can rupt can be checked by reading the contents of the address all devices. The value can be used to determine if the devices should, in theory, respond with an Acknowledge.
Following a Start bit detect, 8 bits are shifted into be set and the slave will begin receiving data after the the SSPSR and the address is compared against the Acknowledge Figure It is also compared to the general call address and fixed in hardware. Address is compared to general call address.
After ACK, set interrupt. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Internal SSPM3: Start bit, Stop bit, Clock Cntl.
Acknowledge Generate SCL. The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required Start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place.
The 4. Address is shifted out the SDA pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. Serial data is slave device and writes its value into the transmitted 8 bits at a time.
Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. In Master Receive mode, the first byte transmitted con- 7. Thus, the first byte transmitted is a 7-bit slave transmitted. Serial data is received 8 bits at a time. Start and Stop conditions indicate the beginning The MSSP module generates an interrupt at the and end of transmission.
Section 9. Interrupt is generated once the Stop condition is complete. The BRG counts down to 0 and stops instruction cycles and the BRG value loaded into until another reload has taken place. The I2Cinterface does not conform to the kHz I2C specification which applies to rates greater than kHz in all details, but may be used with care where higher rates are required by the application.
When the. BRG decrements on Q2 and Q4 cycles. BRG 03h 02h 01h 00h hold off 03h 02h Value. SDA pin is driven low.
When the SCL pin is sam- mode. SDA Note: Following Start condition is complete. If RSEN is programmed while any other event is in progress, it will not take effect. A bus collision during the Repeated Start condition occurs if: A slave sends an Acknowledge when set the Buffer Full flag bit, BF, and allow the Baud Rate it has recognized its address including a general call Generator to begin counting and start the next trans- or when the slave has properly received its data.
Data should be valid before SCL is released high see data setup time specification, Note: The data on the SDA pin will be disregarded. The MSSP the falling edge of the ninth clock.
If the master receives is now in Idle state, awaiting the next command. If not, the bit is set. After the ninth ically cleared. The status of the ACK bit is already set from a previous reception. Following the falling edge of the ninth clock transmis- 9. WCOL must be cleared in software. Start transmit. After Start condition, SEN cleared by hardware. When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge pulled low and the contents of the Acknowledge data bit of the ninth clock.
If the user wishes to gen- will assert the SDA line low. When the Baud Rate Generator starting an Acknowledge sequence. When the SDA pin will be deasserted. The SCL pin is then set. When the SCL pin floats current transfer. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the SSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge condition monitored for arbitration to see if the signal level is at was in progress when the bus collision occurred, the con- the expected output level. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free.
Bus collision has occurred. SDA released by master. At the Figure The reason that bus collision is not a factor pins are monitored. Therefore, one master will always assert SDA before the other. SDA sampled low before Start condition. At the end of the count, counts down to 0. Interrupt cleared in software RSEN. When the pin is sampled high clock arbitration , Bus collision occurs during a Stop condition if: Communications Interface or SCI.
The USART can be configured as a full-duplex asynchronous system that The USART module also has a multi-processor can communicate with peripheral devices, such as communication capability using 9-bit address detection. Clock Source Select bit Asynchronous mode: Synchronous mode: High Baud Rate Select bit Asynchronous mode: Single Receive Enable bit Asynchronous mode: Synchronous mode — Master: Synchronous mode — Slave: Continuous Receive Enable bit Asynchronous mode: This ensures the period of a free running 8-bit timer.
Table shows the formula for computation of the From this, the error in baud rate can be determined. Shaded cells are not used by the BRG. It will reset only when new data is loaded into the bits and one Stop bit. While flag bit TXIF indicates the status is 8 bits. Status bit TRMT frequencies from the oscillator.
The transmitter and receiver empty. No interrupt logic is tied to this bit so the user are functionally independent but use the same data has to poll this bit in order to determine if the TSR format and baud rate.
The baud rate generator register is empty. Parity is not Note 1: The TSR register is not mapped in data supported by the hardware but can be implemented in memory so it is not available to the user. The heart of the transmitter is the Transmit to high-impedance.
The ninth bit must be been transmitted from the previous load. This interrupt can be register. Enable the transmission by setting bit TXEN, follow these steps: If 9-bit transmission is selected, the ninth bit baud rate.
If a high-speed baud rate is desired, should be loaded in bit TX9D. Enable the asynchronous serial port by clearing 8. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9.
Empty Flag. Transmit Shift Reg. Shaded cells are not used for asynchronous transmission. On the detection of The receiver block diagram is shown in Figure The data recovery block is be set. The word in the RSR will be lost. The RCREG actually a high-speed shifter, operating at x16 times the register can be read twice to retrieve the two bytes in baud rate; whereas the main receive serial shifter the FIFO. This is done by resetting the receive logic CREN Once Asynchronous mode is selected, reception is is cleared and then set.
It is, therefore, Register RSR. If the transfer is complete, flag detected as clear. The actual interrupt can be buffered the same way as the receive data. Flag bit RCIF is a read-only bit which is values, therefore, it is essential for the user to read the cleared by the hardware.
This timing diagram shows three words appearing on the RX input. When setting up an Asynchronous Reception, follow 6. Flag bit RCIF will be set when reception is com- these steps: If a high-speed baud rate is desired, 7. RCREG register. If interrupts are desired, then set enable bit 9. If any error occurred, clear the error by clearing RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN. Shaded cells are not used for asynchronous reception.
When setting up an Asynchronous Reception with address detect enabled: This timing diagram shows a data byte followed by an address byte. When transmitting data, pin reverts to a high-impedance state for a reception. In internal clock. The If bit SREN is set to interrupt an on-going transmission Master mode indicates that the processor transmits the and receive a single word , then after the single word is master clock on the CK line.
The DT line will immediately switch from High- The TSR register is not loaded until the last result in an immediate transfer of the data to the TSR bit has been transmitted from the previous load. As register if the TSR is empty. It will reset only when new data is loaded into the 2.
If interrupts are desired, set enable bit TXIE. TRMT is a read- 4. If 9-bit transmission is desired, set bit TX9. No inter- 5.
Enable the transmission by setting bit TXEN. The 6. If 9-bit transmission is selected, the ninth bit TSR is not mapped in data memory so it is not available should be loaded in bit TX9D.
The actual transmission will not occur 8. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock Figure Back-to-back transfers are possible. Shaded cells are not used for synchronous master transmission.
Data When setting up a Synchronous Master Reception: If both bits are 2. Enable the synchronous master serial port by set, CREN takes precedence. When the transfer is complete, interrupt flag bit, RCIF 4.
Flag bit RCIF is a read-only bit which is 6. If a single reception is required, set bit SREN. RCREG register has been read and is empty. The 7. It is possible for two bytes of data to be enable bit RCIE was set. On the enabled and determine if any error occurred clocking of the last bit of the third byte, if the RCREG during reception. Bit OERR has to be cleared in If any error occurred, clear the error by clearing software by clearing bit CREN.
Shaded cells are not used for synchronous master reception. Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at 1.
This allows the device to transfer or CSRC. Slave mode is 2. If 9-bit transmission is desired, then set bit TX9. SLEEP instruction is executed, the following will occur: TSR register and transmit. Shaded cells are not used for synchronous slave transmission.
The operation of the Synchronous Master and Slave 1. If receive is enabled by setting bit CREN prior to the 2. If interrupts are desired, set enable bit RCIE. SLEEP instruction, then a word may be received during 3. If 9-bit reception is desired, set bit RX9.
On completely receiving the word, the RSR reg- 4. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is enable bit RCIE bit is set, the interrupt generated will complete and an interrupt will be generated if wake the chip from Sleep.
If the global interrupt is enable bit RCIE was set. If any error occurred, clear the error by clearing bit CREN. Shaded cells are not used for synchronous slave reception. These registers are: The port pins can be configured or RA3. Reference Manual DS Do not select any unimplemented channels with these devices. On any device Reset, the port pins that are multiplexed with analog functions ANx are forced to be an analog input.
Wait the required acquisition time. Start conversion: To determine sample time, see Section The To calculate the minimum acquisition time, analog input model is shown in Figure The source Equation may be used.
The sampling switch to meet its specified resolution. As the Manual DS The reference voltage VREF has no effect on the equation since it cancels itself out. The maximum recommended impedance for analog sources is 2. This is required to meet the pin leakage specification. If the TRIS bit is cleared output , the digital software selected. AN0 of 1. TAD vs.
For extended voltage devices LF , please refer to Section This register pair is 16 bits wide. Right Justified Left Justified. To allow the con- ADCS1: When the conver- These registers are not available on pin devices. A block diagram The comparator module contains two analog compara- of the various comparator configurations is shown in tors.
The inputs to the comparators are multiplexed Figure The on-chip volt- age reference Section CM0 bit settings. Figure shows the eight possible modes. If the Comparator Otherwise, a false interrupt may occur. Section In this the output of the comparator in Figure represent mode, the internal voltage reference is applied to the the uncertainty due to input offsets and response time. The new reference voltage or input source, before the com- analog signal present at VIN- is compared to the signal parator output has a valid level.
Otherwise, the maximum delay of the comparators should be used Section These bits are read-only. When enabled, multiplexors in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the com- parator. Figure shows the comparator output block diagram. When reading the Port register, all pins Pins configured as digital inputs will comparator module can be configured to have the com- convert an analog input according to the parators operate from the same or different reference Schmitt Trigger input specification.
However, threshold detector applications may 2: Analog levels on any pin defined as a dig- require the same reference. The reference signal must ital input may cause the input buffer to be between VSS and VDD and can be applied to either consume more current than is specified. When used as an output, a pull-up resistor is required. The interrupt in the following manner: If any of these bits are allow flag bit CMIF to be cleared.
Since the analog pins are connected to a interrupt is functional if enabled.
This interrupt will digital output, they have reverse biased diodes to VDD wake-up the device from Sleep mode when enabled. If the input voltage deviates from this currents than shown in the power-down current range by more than 0.
Each operational comparator diodes is forward biased and a latch-up condition may will consume additional current as shown in the com- occur. To minimize power consumption ommended for the analog sources. Shaded cells are unused by the comparator module. A programmable register controls the function of The output of the reference generator may be con- the reference generator.
The primary purpose of this mented to provide two ranges of CVREF values and has function is to provide a test path for testing the a power-down function to conserve power when the reference generator function.
The comparator reference.
Shaded cells are not used with the comparator voltage reference. The RC oscillator power saving operating modes and offer code option saves system cost while the LP crystal option protection. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up.
It is designed to keep the part in Reset while the power supply stabilizes. With these two timers on-chip, most applications need no external Reset circuitry. Use of a series cut crystal may give a frequency out 2. When in 4. See Table and Table for recommended values of C1 and C2. A series resistor Rs may be required for AT strip cut crystals. RF varies with the crystal chosen. Range Cap. Range option offers additional cost savings.
In addition to this, the oscillator kHz 15 pF 15 pF frequency will vary from unit to unit due to normal pro- XT kHz pF pF cess parameter variation. Higher capacitance increases the stability of oscillator but also increases the start-up time. Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification.
They are not affected by a WDT of Reset: Some registers are not affected in any Reset condition. Their status is unknown on POR and unchanged in any other Reset. Enable PWRT. V REF module. Special Microcontroller Features: CMOS Technology: Program Memory. Single Word. PIC16FA 7. PIC16FA DSC-page 1.
This document contains device specific information. All devices in the. The available features are summarized in Table The pinouts for these.
Range Reference Manual DS , which may be. The Refer-. TABLE Key Features. Operating Frequency. Resets and Delays.
Flash Program Memory. Data Memory bytes. Serial Communications. DC — 20 MHz. Ports A, B, C. Parallel Communications. Analog Comparators.